1. Field of the Invention
The present invention relates to techniques for partitioning the design of an integrated circuit (IC) chip into smaller design blocks.
2. Related Art
Advances in semiconductor technology presently make it possible to integrate large-scale systems, including tens of millions of transistors, onto a single semiconductor chip. Integrating such large-scale systems onto a single semiconductor chip increases the speed at which such systems can operate, because signals between system components do not have to cross chip boundaries, and are not subject to lengthy chip-to-chip propagation delays. Moreover, integrating large-scale systems onto a single semiconductor chip significantly reduces production costs, because fewer semiconductor chips are required to perform a given computational task.
However, as integrated circuit (IC) designers integrate more system components onto a single chip, IC designs are reaching and exceeding the limits of the IC design tools, specifically the logic optimization and detailed place-and-route tools. For instance, Synopsys Physical Compiler®, Synopsys Astro®, and Synopsys Galileo® have capacity limits of approximately one million instances. For larger IC designs, the IC designer must partition the design into smaller design blocks, called “soft macros” or “physical partitions,” using a floorplanner such as Synopsys JupiterXT®. Each soft macro or physical partition contains a set of logical modules of the design. When using a floorplanner such as JupiterXT®, the IC designer must manually partition the design. Other floorplanning tools employ techniques to automatically partition the design to minimize pin count.
As chip designs become larger, the task of manually or automatically partitioning a chip into physical partitions, while accounting for timing and pin count constraints, becomes progressively more difficult. Cells belonging to different physical partitions are placed, optimized, and routed within their own disjoint layout areas, which can result in inter-block wires that are longer than intra-block wires. Since wire delay dominates the overall chip delay, these longer intra-block wires can have an adverse effect on circuit timing.
FIG. 1A illustrates an exemplary partitioning of a layout containing cells 102, 104, 106, 108, 110, 112, 114, and 116. The lines between these cells indicate which cells communicate with each other.
One technique for partitioning an IC design is to reduce the inter-partition wires by searching for a “min-cut” line. This technique is analogous to reducing pin count in a partition. Using this technique, cells 102, 104, 112 and 114 are placed in one partition, and cells 106, 108, 110, and 116 are placed in another partition.
FIG. 1B illustrates an exemplary placement of cells within a chip 100 which is divided into two partitions. Chip 100 contains the same cells as in FIG. 1A as well as wires 118, 120, 122, 124, 126, 128, 130, 132, and 134. FIG. 1B also illustrates min-cut line 136. The place-and-route tool places and routes each partition of the chip separately. As a result, the placement and routing in each partition is optimized, but the placement and routing between the partitions is not optimized. For instance, since cells 110 and 116 communicate with each other, the place-and-route tool places cells 110 and 116 close together, making wire 134 relatively short. Similarly, since cells 112 and 114 communicate with each other, the place-and-route tool places cells 112 and 114 close together, making wire 128 relatively short.
However, cell 116 also communicates with cell 112. Since each partition was placed and routed separately, wire 126, which connects cells 112 and 116 is relatively long, which may cause timing problems.
Hence, what is needed is a method and an apparatus for automatically partitioning an IC layout without the problems described above.